ST Ericsson has posted a video describing their new Fully Depleted Silicon On Insulator FET technology (FD-SOI). It's a planar technology that incorporates a insulating layer under the source, drain, and channel of the FET. The advantage of this approach is that little or no channel dopents are used lowering the FET-to-FET variations, and it lowers leakage currents making devices much lower power than devices using bulk FET structures. A back gate is also included and used in combination with the top gate to allow control of the the FET performances for either high speed or low power. The FD-SOI process is now available at the 28 nm node and the 14 nm is presently in development.